Large electronic systems, as used in computing, data networking, and telecommunications elements, often use a common backplane to provide high speed interconnection between several circuit boards, packs or modules that plug into slots in the backplane. The backplane is typically constructed of a multi-layer circuit board with conductive traces selectively routed to provide the high-speed interconnection. Connectors are provided on the backplane to couple circuit boards, packs, or modules which are held in place using a slotted chassis. The properties of these backplanes often have large influence over the capacity, performance, reliability, cost, and scale properties of electronic systems. Some backplane designs provide high capacity, while others provide low cost.
A number of factors must be considered in backplane design including, functionality, connector density, number of layers required and electrical characteristics, including crosstalk, signal attenuation, reflections, and transmission line effects. The electrical characteristics are affected by trace length (attenuation) and any vias (parasitic capacitance) in the signal path.
Currently, there are two predominant architectures for providing backplane transport infrastructures in high-speed telecommunications platforms: the bus and the fabric. These architectures both have limitations preventing the creation of a truly universal platform.
Bus-based backplanes use a large set of parallel signals, where each signal typically touches each slot and hence each board. This interconnection scheme is versatile and low cost, but imposes practical limits of a few billion bits per second on the maximum system throughput and also limits reliability. The total throughput must also be shared among all boards on the backplane. Buses are typically used in smaller systems that do not process large amounts of broadband traffic, or in systems with severe cost constraints. In particular, bus-based backplanes have a very low cost of common elements, and therefore permit low system costs, especially where a system is not equipped with all of its circuit cards or modules initially.
Fabric based systems use a central high-speed fabric or hub to switch traffic between all modules. High-speed point-to-point connections (either parallel or serial) are routed over a cable or backplane between each module and the central fabric, in a star topology. The central fabric can provide the large bandwidths (over 1 trillion bits per second) needed to support high-speed computing or broadband communications. Unfortunately, because the full central fabric, with support for the maximum number of connections, must be installed before any modules can be interconnected, the cost of such a system is often quite high, especially for partially equipped systems, where the large cost of the fabric is only amortized over a few modules.
A prior art backplane design provides a plurality of slots, with each slot being adapted to receive a blade or circuit pack. This prior art backplane design is commonly used in a star configuration where all slots route to one or more particular slots, which are used, for example, for the central fabric. For this configuration, the circuit packs or blades are designed in such a manner, that any board may operate in any slot. More specifically, a particular physical interface on the board is always the interface for a particular slot to reach the central fabric. For example, connector pins A2 are always the interface for connection to the board in slot 1, regardless of which slot the board is in. In other words, for every board, no matter which backplane slot it is in, connector pins A2 provide the physical path to slot 1 (e.g., the central fabric). Therefore, whenever circuitry on the board needs to communicate with the board in slot 1, regardless of which slot the board is plugged into, pins A2 provide the interface to slot 1.
When another configuration, such as a mesh configuration (each board communicates directly to every other board) is used instead of the star configuration, the backplane routing becomes very complicated. In particular, if the backplane is designed such that any board communicates with another board based on a mapping of rows to slots without regard to the location of the sending board, as in the star configuration described above, then vertical as well as horizontal routing is typically required and trace length is increased. This is undesirable, since in Manhattan style routing, vertical and horizontal routing are on different layers. Each layer adds cost and increases backplane thickness and weight. In addition, having to route a signal between horizontal and vertical routing requires more vias, which also adds to the cost and reduces performance. And, the longer traces required adversely affect performance. FIG. 1 illustrates the problem of routing a mesh configuration using traditional backplane slot-independent routing.
The backplane 100 illustrated in FIG. 1 has six slots 102a–f for receiving circuit packs. Each slot 102 has six rows 104a–f, with interfaces for making routing connections. In the example shown in FIG. 1, each row has a receiver pin, identified with the letter “R,” and a transmitter pin, identified with the letter “T.” Note that the “T” and “R” each represent a differential pair. That is, there are two pins and traces associated with “T” and two pins and traces associated with “R.” In this example, there is only one routing channel 106 per layer between each row. However, an additional routing channel per layer is available above the top row and an additional routing channel per layer is available below the bottom row. Each routing channel accommodates a differential signal pair.
In FIG. 1, each row 104 for a slot 102 is connected via backplane routing (illustrated by the lines with arrows) to the slot corresponding to the row. In other words, row one 104a is the interface to slot one (102a). More specifically, top row 104a of each slot (102a–f) is associated with slot one in the backplane. That is, backplane routing associates and connects the top row 104a of slot two (102b) to the second row 104b of slot one (102a). Similarly, the top row 104a of slot three (102c) is connected via backplane routing to row three 104c of slot one(102a). This pattern continues with row one 104a of slot six (102f) being interconnected to row six 104f of slot one 102a. There is no routing required in the backplane to connect row one of slot one to itself, because this interface can be accounted for directly on the circuit pack. Alternatively, routing can be provided in the backplane to connect the transmitter and receiver of row one to each other. Or, these pins may be used to provide a geographic address or slot number.
In an analogous manner to that described above with respect to row one 104a and slot one 102a, row two 104b is the interface for slot two 102b. This pattern continues, and finally, row six 104f is the interface for slot six 102f. In other words, row X of slot Y is interconnected to row Y of slot X.
Traditional backplane routing, as applied to the mesh configuration, is undesirable and costly. Generally, in such an arrangement, for N slots, N layers are required, unless extra vias are used. For the six slot example shown in FIG. 1, six routing layers and six rows are required to maintain symmetry in the routing. And vertical routing is required. See the routing congestion between slots 102c and 102d in FIG. 1.
Therefore a need exists for a novel backplane configuration that minimizes backplane trace length, minimizes layers and also minimizes the number of vias required.